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Simple, Synchronous Voltage Mode PWM Controller
POWER MANAGEMENT Draft Description
The SC2608B is a versatile voltage-mode PWM controller designed for use in step down DC/DC power supply applications. A simple, fixed frequency, highly efficient buck regulator can be implemented using the SC2608B with minimal external components. The input voltage range is from +5V to +12V. Internal level shift and drive circuitry eliminates the need for an expensive P-channel, high-side MOSFET. The small device footprint allows for compact circuit design. SC2608B features include temperature compensated voltage reference, triangle wave oscillator, current limit comparator, and an externally compensated error amplifier. Current limit is implemented by sensing the voltage drop across the bottom MOSFET RDS(ON). The SC2608B operates at a fixed frequency of 250kHz providing an optimum compromise between efficiency , external component size, and cost. SC2608B has a thermal protection circuit, which is activated if the junction temperature exceeds 150 OC.
SC2608B
Features
+5V or +12V input voltage 250kHz operation High efficiency (>90%) 1.25% Voltage feedback accuracy over temperature Hiccup mode over current protection 1.2A output drive RDS(ON) Current sensing for protection Industrial temperature range Available in SO-8 package Integrated boot strap diode Thermal Shut down Fully WEEE and RoHS Compliant
Applications
Termination supplies Low cost microprocessor supplies Peripheral card supplies Industrial power supplies High density DC/DC conversion
Typical Application Circuit
Figure 1
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SC2608B
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
P ar am et er VCC to GN D BST to PHASE BST to GN D PHASE to GN D (note1) DH to PHASE
(note1)
S y m b ol
M ax i m u m +20 +15 +20 -1 to +24 +15 -1 to +15 +7 +7
Units V V V V V V V V
O
DL to GN D (note2) COMP/SS to GN D SEN SE to GN D Thermal Resistance Junction to Case (SO-8) Thermal Resistance Junction to Ambient (SO-8) Operating Temperature Range Storage Temperature Range ESD Rating (Human Body Model) JC JA TJ TSTG ESD
40 120 -40 to +125 -65 to +150 4
C/W C/W
O
O
C C
O
kV
Note 1: Under pulsing condition, the peak negative voltage can not be lower than -3.6V with less than 20nS from 50% to 50%. Note 2: Under pulsing condition, the peak negative voltage can not be lower than -5V with less than 20nS from 50% to 50%.
Electrical Characteristics
Unless specified: VCC = 12V, VBST - VPhase = 12 V, VOUT = 3.3V, TJ = TA = 25oC.
P ar am et er P ow er S u p p l y Sup p ly Voltage Sup p ly Current U n d er v ol t ag e L ock ou t UVLO Threshold Hysteresis E rror A m p l i f i er Feedback Voltage
S y m b ol
Con d i t i on s
Min
Ty p
M ax
Units
VCC ICC VCOMP < 0.4V
4 6
14 6.5
V mA
V th V hys
0< TJ < 85OC
3.75 80
3.85
V mV
V FB
4.5V0.787 0.79
0.797 0.8
0.807 0.81
V V
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SC2608B
POWER MANAGEMENT Electrical Characteristics
Unless specified: VCC = 12V, VBST - VPhase = 12 V, VOUT = 3.3V, TJ = TA = 25oC.
P ar am et er E/A Transconductance Op en Loop DC Gain Inp ut Bias Current Outp ut Sink Current Outp ut Source Current O sci l l at or Switching Frequency Ramp Peak Voltage Ramp Valley Voltage Maximum Duty Cycle M O S F E T Dri vers DH Sink/Source Current DL Sink/Source Current DH Rise/Fall Time DL Rise/Fall Time Dead Time DL Minimum On Time Cu rren t L i m i t Trip Voltage S of t - S t ar t SS Source Current SS Sink Current T h er m al S h u t d ow n Over Temp erature Trip Point
S y m b ol Gm AO IFB ISINK ISOURCE
Con d i t i on s
Min
Ty p 7 60 1
M ax
Units mS dB
3
uA uA uA
VSENSE > 0.9V; VCOMP = 2.1V VSENSE < 0.7V; VCOMP = 2.1V
-800 120
FOSC V P -K VV DMAX
Vcc =12V 4.75V < VCC < 12.6V 4.75V < VCC < 12.6V
225
250 1.8 0.8 85
275
kHz V V %
IDH IDL tr, tf tr, tf td t tON
tPW > 400nS VGS = 4.5V (src) VGS = 2.5V (snk) CL = 3000p F, See Fig. 2 CL = 4000p F, See Fig. 2 See Fig. 2 4.75V < Vcc < 12.6V
1.2 1.2 50 50 65 440
A
A ns ns ns ns
V T R IP
4.75V < Vcc < 12.6V Vtrip = VPHASE - GN D
-575
-500
-425
mV
ISRC ISNK
VCOMP < 2.5V VCOMP > 0.5V
4 -4
uA uA
TOTP
150
o
C
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SC2608B
POWER MANAGEMENT Pin Configuration
Top View
Ordering information
Devi ce
( 1)
Package SO-8 Eval u ati on B oard
SC2608B STRT(2)
BST DH GND DL
1 2 3 4
8 7 6 5
(8-Pin SO-8)
PHASE COMP/SS SENSE VCC
SC2608B EV B
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) This device is fully WEEE and RoHS Compliant
Pin Descriptions
Pin # 1 2 3 4 5 6 P i n N am e BST DH GN D DL VCC Sense COMP/SS PHASE Bootstrap for high side driver. High side driver outp ut. Ground. Low side driver outp ut. Chip bias sup p ly p in. Outp ut voltage sense inp ut. Error amp lifier outp ut. Connect comp ensation network to GN D. The comp ensation cap acitor serves as soft star t cap acitor. By p ulling this p in low will disable the outp ut. Connect this p in to the switching node between the MOSFETs. P i n Fu n c t i o n
7
8
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SC2608B
POWER MANAGEMENT Gate Drive Timing Diagram
Figure 2
Block Diagram
VCC
BST DH PHASE
OSC S + REF 0.8V R Q
LEVEL SHIFT
E/A
+
NON-OVERLAP TIMING
SENSE
PWM
-
0
VCC OCP & UVLO
Vcc DL
OCP
GND
PHASE
0
+ -
0 0
COMP/SS
Figure 3
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SC2608B
POWER MANAGEMENT Theory of Operation
Synchronous Buck Converter The output voltage of the synchronous converter is set and controlled by the output of the error amplifier. The inverting input of the error amplifier receives its voltage from the SENSE pin. The non-inverting input of the error amplifier is connected to an internal 0.8V reference. The error amplifier output is connected to the compensation pin. The error amplifier generates a current proportional to (0.8V-Vsense), which is the COMP pin output current (Transconductance ~ 7mS). The voltage on the COMP pin is the integral of the error amplifier current. The COMP voltage is the non-inverting input of the PWM comparator and controls the duty cycle of the MOSFET drivers. The compensation network controls the stability and transient response of the regulator. The larger capacitor, the slower COMP voltage changes, and slower the duty cycle changes. The non-inverting input voltage of the PWM comparator is the triangular ramp signal generated from the oscillator. The peak-to-peak voltage of the ramp is 1V, this is a parameter used in control loop calculation. When the oscillator ramp signal rises above the COMP voltage, the comparator output goes high and the PWM latch is reset. This pulls DH low, turning off the high-side MOSFET. After a short delay (dead time), DL is pulled high, turning on the low-side MOSFET. The oscillator also produces a set pulse for the PWM latch to turn off the low-side MOSFET, After a delay time, DH is pulled high to turn on the high-side MOSFET. The delay time is determined by a monostable on the chip. The triangle wave minimum is about 0.8V, and the maximum is about 1.8V. Thus, if Vcomp = 0.7V, high side duty cycle is the minimum (~0%) , but if Vcomp is 1.8V, duty cycle is at maximum ( ~90%).The internal oscillator uses an on-chip capacitor and trimmed precision current sources to set the oscillation frequency to 250kHz. Figure 1 shows a 2.5V output converter. If the Vout <2.5V, then the SENSE voltage < 0.8V. In this case the error amplifier will be sourcing current into the COMP pin so that COMP voltage and duty cycle will gradually increase.If Vout > 2.5V, the error amplifier will sink current and reduce the COMP voltage, so that duty cycle will decrease.The circuit will be in steady state when Vout =2.5V , Vsense = 0.8V, Icomp = 0. The COMP voltage and duty cycle depend on Vin. outputs remain in the off state whenever the supply voltage drops below the set threshold. Lockout occurs if VCC falls below 3.6V typ. Soft Start The SC2608B provides a soft start function to prevent large inrush currents upon power-up or hiccup retry. If both COMP and SENSE pins are low (<300mV), the device enters soft start mode, and the compensation capacitor is slowly charged by an internal 4uA current source. When the COMP pin reaches 300mV, the low side FET is switched on in order to refresh the bootstrap capacitor, and begin PWM from a known state. As the COMP pin rises above 800mV, PWM begins at minimum duty cycle. COMP continues to charge, slowly sweeping the device through the duty cycle range until FB reaches the regulation point of 800mV. Once FB reaches the regulation point, the soft start current is switched off, and the strong error amp is enabled, providing a glitch-free entrance into closed loop operation. The overcurrent comparator is still active during soft start mode, and will override soft start in the event that an overcurrent is detected, such as startup into a dead short. R DS(ON) Current Limiting In case of a short circuit or overload, the low-side (LS) FET will conduct large currents. To protect the regulator in this situation, the controller will shut down the regulator and begin a soft start cycle later. While the LS driver is on,the Phase voltage is compared to the OCP trip voltage. If the phase voltage is lower than OCP trip voltage, an over current condition is detected. The low-side Rdson sense is implemented at end of each LS-FET turn-on duration. The minimum turn-on time of the LS-FET is set to be 400nS. This will ensure the sampled signal is noise free by giving enough time for the switching noise to die down.
OCP Hiccup In the event that an overcurrent is detected, the SC2608B latches the fault and begins a hiccup cycle. Switching is immediately stopped, and the drivers are set to a tristate condition (Both DH and DL are low). COMP is slowly discharged to 300mV with an internal 4uA current source, providing a long cooldown time to keep power dissipation low in the event of a continuous dead short. Once COMP and SENSE both fall below the 300mV threshold, the part Voltage Lockout U nder V oltage Lock out re-enables the 4uA soft start current , and the device begins The under voltage lockout circuit of the SC2608B as- a normal startup cycle again. sures that both high-side and low-side MOSFET driver
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SC2608B
POWER MANAGEMENT Applications Information (Cont.)
A note to the user is needed: The device cannot restart until both COMP and SENSE are low, to prevent start up into a charged output. In the event of an overcurrent condition, the output is quickly discharged by the load, therefore bringing SENSE below the 300mV threshold. If the COMP pin is pulled low by an external device (such as an open-drain logic gate used for system shutdown), and SENSE is high(above 300mV) while COMP is low, then the SC2608B turns on the low side FET to discharge the output before changing to shutdown or soft-start mode. The low side FET turns off when SENSE drops below 300mV and the converter remains in the tri-state condition until COMP is released. Although this shutdown technique can be used successfully on the SC2608B, the system designer using COMP for external shutdown will need to consider the load on the low side FET when discharging the output capacitor bank. For large capacitor bank, this peak current can be quite large as it is limited only by the RDS(ON) of the low side FET. Fortunately the duration of this event is quite short, and has been shown in the lab to have no detrimental effect on the performance of the external FETs. Disabling the output by pulling down COMP/SS pin is only recommended when the output capacitor bank is not too large. Compensation Network Design
G pwm =
1 Vramp
where the ramp amplitude is fixed at 1 volts. The total control loop-gain can then be derived as follows:
V 1 + sRcCo T (s ) = Gm * G pwm * Vin * bg * H c (s ) * V R L o 1 + s RcCo + + s 2 LCo 1 + c R Ro o
H c (s ) = 1 1 R+ 1 sC + sC i
The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: (1) Calculate the corner frequency of the output filter:
Fo = 2
(2) Calculate the ESR zero frequency of the output filter capacitor:
Fesr = 1 2 R c C o
F SW 5
1 LC o
(3) Check that the ESR zero frequency is not too high.
F esr <
E/A
VBG 0.8V
G_PWM
L Rc VIN Ro
R Ci C
R1 R2
Co
Fig. 4. SC2608B small signal model.
The control model of SC2608B is depicted in Fig. 4. This model can also be used to generate loop gain Bode plots. The bandgap reference is 0.8V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed 0 . 007 A gain of:
Gm =
If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency : 1 FX _ OVER = * FSW 5 If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as: when
V F F 1 R= * esr * X _ OVER * o F F Gpwm *Vin * Gm o esr Vbg
2
The compensation network includes a resistor and a capacitor in series, which terminates the output of the error amplifier to the ground. The PWM gain is inversion of the ramp amplitude, and this gain is given by:
V
F o < F esr <
F sw 5
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SC2608B
POWER MANAGEMENT Applications Information (Cont.)
(5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency:
F zero
C=
An example is given below to demonstrate the procedure introduced above. Vin=12V Vo=2.5V Io=15A Fsw=250KHz L=2.2uH set C i=1nF Rc=1.33K C=327.95nF set to Rc=1.5K set to C=100nF C o=4400uF R c=0.009 Vbg=0.8V Vramp=1V Gm=0.007A/V
F =o 5
1 2R * Fzero
SC2608B soft start time is determined by the compensation capacitor. Capacitance can be adjusted to satisfy the soft start requirement. (6) The final step is to generate the Bode plot by using the simulation model in Fig. 4 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot.
100
for suitable soft start time
Loop Gain Mag (dB)
50 mag( i) 0
50 10 100
1 .10
3
1 .10 Fi
4
1 .10
5
1 .10
6
Loop Gain Phase (Degree)
0
45
phase ( i) 90
135
180 10 100
1 .10
3
1 .10 Fi
4
1 .10
5
1 .10
6
Fig. 5. Bode plot of the loop
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SC2608B
POWER MANAGEMENT Application Information Typical Typical Application Schematic
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Qu an ti ty 1 2 1 2 1 2 3 1 1 1 1 1 2 2 1 Referen ce C1 C2,C3 C4 C5,C13 C6 C7,C8 C9,C10,C11 C12 L1 Q1 Q2 R2 R3,R6 R4,R5 U1 Par t 4.7u F/16V 1500u F/16V 100p F/50V 1u F/16V 68n F/25V 2200u F/6.3V 4.7u F/6.3V 2.2n F 1.2u H IPD09N 03LA IPD13N 03LA 1K 1K, 1% 1R0 SC2608B Ven d er Yageo Pan ason i c FJ Yageo Yageo Yageo Pan ason i c FJ Yageo Yageo 3L COILS In fi n eon In fi n eon Yageo Yageo Yageo SEMTECH
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SC2608B
POWER MANAGEMENT Application Information
Typical Typical DDR VDDQ Application Schematic
5VDual
Q1 IP B 09N 03LA
C1 4.7uF /16V
C2 1500uF /16V
C3 1500uF /16V
C4 1500uF /16V
C5 100pF
U1 8 7 Phase BST 1 2 3 4 C6 1uF/16V Q2 IPB09N 03LA R4 2R2 C14 1n L1 1.2uH/40A C8 1800uF /6.3V C9 1800uF /6.3V C10 1800uF /6.3V C11 4.7uF /6.3V C12 4.7uF /6.3V
1.8VOUT/24A
6 5
SENSE GND VCC SC2608B DL
4.7uF /6.3V
R2 1k 5VDual
C7 68nF Sense
COMP/SS DH
C13
R3 1.27k Sense R5 1k
D1 BAT54H D2 1N4148 +12V
C15 1uF/16V
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Qu an ti ty 4 3 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 Referen ce C1,C11,C12,C13 C2,C3,C4 C5 C6,C15 C7 C8,C9,C10 C14 D1 D2 L1 Q1 Q2 R4 R2 R3 R5 U1 Par t 4.7u F/6.3V 1500u F/6.3V 100p F/50V 1u F/16V 68n F/25V 1800u F/6.3V 1n F/50V B AT54H 1N 4148 1.2u H/40A IPD09N 03LA IPD09N 03LA 2R2, 5% 1K, 5% 1.27K, 1% 1K, 1% SC2608B Ven d er Yageo Pan ason i c FJ Yageo Yageo Yageo Pan ason i c FJ Yageo Yageo Fai rch i l d 3L COILS In fi n eon In fi n eon Yageo Yageo Yageo Yageo SEMTECH
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SC2608B
POWER MANAGEMENT Outline Drawing - SO-8
A e N 2X E /2 E1 E D
D IM
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc
D IM E N S IO N S M IL L IM E T E R S IN C H E S M IN N O M M A X M IN N O M M A X
.0 6 9 .0 1 0 .0 6 5 .0 2 0 .0 1 0 .1 9 3 .1 9 7 .1 5 4 .1 5 7 .2 3 6 B S C .0 5 0 B S C .0 1 0 .0 2 0 .0 4 1 .0 1 6 .0 2 8 (.0 4 1 ) 8 8 0 .0 0 4 .0 1 0 .0 0 8 .0 5 3 .0 0 4 .0 4 9 .0 1 2 .0 0 7 .1 8 9 .1 5 0 1 .3 5 0 .1 0 1 .2 5 0 .3 1 0 .1 7 4 .8 0 3 .8 0 1 .7 5 0 .2 5 1 .6 5 0 .5 1 0 .2 5 4 .9 0 5 .0 0 3 .9 0 4 .0 0 6 .0 0 B S C 1 .2 7 B S C 0 .2 5 0 .5 0 0 .7 2 1 .0 4 0 .4 0 (1 .0 4 ) 8 0 8 0 .1 0 0 .2 5 0 .2 0
1 ccc C 2 X N /2 T IP S
2 e /2 B D
aaa S E A T IN G PLANE
C A2 A h h H C A -B D GAGE PLANE 0 .2 5 S E E D E T A IL S ID E V IE W L (L 1 ) D E T A IL c
C bxN bbb
A1
01
A
A
NO TES: 1. 2. 3. C O N T R O L L IN G D IM E N S IO N S A R E IN M IL L IM E T E R S (A N G L E S IN D E G R E E S ). DATUM S -A AND -B T O B E D E T E R M IN E D A T D A T U M P L A N E -H -
D IM E N S IO N S "E 1 " A N D " D " D O N O T IN C L U D E M O L D F L A S H , P R O T R U S IO N S OR GATE BURRS.
Land Pattern - SO-8
X
D IM
(C ) G Z C G P X Y Z
D IM E N S IO N S IN C H E S M IL L IM E T E R S
( .2 0 5 ) .1 1 8 .0 5 0 .0 2 4 .0 8 7 .2 9 1 (5 .2 0 ) 3 .0 0 1 .2 7 0 .6 0 2 .2 0 7 .4 0
Y P
NO TES: 1. T H IS L A N D P A T T E R N IS F O R R E F E R E N C E P U R P O S E S O N L Y . C O N S U L T Y O U R M A N U F A C T U R IN G G R O U P T O E N S U R E Y O U R C O M P A N Y 'S M A N U F A C T U R IN G G U ID E L IN E S A R E M E T . R E F E R E N C E IP C -S M - 7 8 2 A , R L P N O . 3 0 0 A .
2.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 (c) 2007 Semtech Corp.
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